Memory links are multi-drop buses that are operated either between a memory controller and a memory chip or directly between the processor and a memory chip. The memory is typically composed of a set of dual inline memory modules (DIMMs) that each has one or more ranks of memory. Because of the T-junctions and the different impedance levels required to operate the multi-drop bus, memory channels typically have a long pulse response with many reflections. These non-idealities either limit the maximum data rate or call for sophisticated equalization schemes.